The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Oct. 18, 2013
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Wei-Chih Chen, Kaohsiung, TW;

Chung-Hsien Tsai, Tainan, TW;

Tung-Ming Chen, Kaohsiung, TW;

Chih-Sheng Chang, Kaohsiung, TW;

Jun-Chi Huang, Taichung, TW;

Chih-Jen Lin, Kaohsiung, TW;

Yu-Hsiang Lin, New Taipei, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28052 (2013.01); H01L 21/28114 (2013.01); H01L 29/6659 (2013.01); H01L 21/2652 (2013.01); H01L 29/42372 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/7843 (2013.01); H01L 29/7847 (2013.01);
Abstract

A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.


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