The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Jun. 17, 2011
Sheng-hsiung Wang, Zhubei, TW;
Hsien-chin Lin, Hsinchu, TW;
Yuan-ching Peng, Hsinchu, TW;
Chia-pin Lin, Xinpu Township, TW;
Fan-yi Hsu, Toufen Town, TW;
Ya-jou Hsieh, Xizhou Township, TW;
Sheng-Hsiung Wang, Zhubei, TW;
Hsien-Chin Lin, Hsinchu, TW;
Yuan-Ching Peng, Hsinchu, TW;
Chia-Pin Lin, Xinpu Township, TW;
Fan-Yi Hsu, Toufen Town, TW;
Ya-Jou Hsieh, Xizhou Township, TW;
Abstract
A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.