The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Jul. 03, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Hao Chen, Hsin-Chu, TW;

Long Hua Lee, Taipei, TW;

Chun-Hsing Su, New Taipei, TW;

Yi-Lin Tsai, Tainan, TW;

Kung-Chen Yeh, Taichung, TW;

Chung Yu Wang, Hsin-Chu, TW;

Jui-Pin Hung, Hsin-Chu, TW;

Jing-Cheng Lin, Chu Tung Zhen, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/40 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 29/0657 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/81 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/26145 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83104 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/351 (2013.01);
Abstract

A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.


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