The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Jul. 29, 2014
Efficient Power Conversion Corporation, El Segundo, CA (US);
Stephen L. Colino, Bear, DE (US);
Jianjun Cao, Torrance, CA (US);
Robert Beach, La Crescenta, CA (US);
Alexander Lidow, Marina Del Rey, CA (US);
Alana Nakata, Redondo Beach, CA (US);
Guangyuan Zhao, Torrance, CA (US);
Yanping Ma, Torrance, CA (US);
Robert Strittmatter, Tujunga, CA (US);
Michael A. De Rooji, Palm Springs, CA (US);
Chunhua Zhou, Torrance, CA (US);
Seshadri Kolluri, San Jose, CA (US);
Fang Chang Liu, Toufen Township, TW;
Ming-Kun Chiang, Hsinchu, TW;
Jiali Cao, Torrance, CA (US);
Agus Jauhar, Hsinchu, TW;
Efficient Power Conversion Corporation, El Segundo, CA (US);
Abstract
A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.