The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Mar. 03, 2011
Venkatesh Sundaram, Alpharetta, GA (US);
Fuhan Liu, Atlanta, GA (US);
Rao Tummala, Greensboro, GA (US);
Vijay Sukumaran, Atlanta, GA (US);
Vivek Sridharan, Atlanta, GA (US);
Qiao Chen, Atlanta, GA (US);
Venkatesh Sundaram, Alpharetta, GA (US);
Fuhan Liu, Atlanta, GA (US);
Rao Tummala, Greensboro, GA (US);
Vijay Sukumaran, Atlanta, GA (US);
Vivek Sridharan, Atlanta, GA (US);
Qiao Chen, Atlanta, GA (US);
GEORGIA TECH RESEARCH CORPORATION, Atlanta, GA (US);
Abstract
Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.