The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Sep. 21, 2012
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Chia-En Huang, Hsinchu, TW;
Yi-Hung Tsai, Hsinchu, TW;
Chih-Chieh Chiu, Hsinchu, TW;
Hsiao-Lan Yang, Taipei, TW;
I-Han Huang, Tainan, TW;
Chun-Jiun Dai, Taichung, TW;
Fu-An Wu, Hsinchu, TW;
Hong-Chen Cheng, Hsinchu, TW;
Jung-Ping Yang, Jui-bei, TW;
Cheng Hung Lee, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Abstract
One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example.