The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Feb. 11, 2013
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Ralf Otremba, Kaufbeuren, DE;

Josef Hoeglauer, Heimstetten, DE;

Juergen Schredl, Mering, DE;

Xaver Schloegel, Sachsenkam, DE;

Klaus Schiess, Allensbach, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 27/088 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49844 (2013.01); H01L 24/34 (2013.01); H01L 25/071 (2013.01); H01L 25/072 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01);
Abstract

Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.


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