The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2015
Filed:
Jul. 02, 2014
Efficient Power Conversion Corporation, El Segundo, CA (US);
Chunhua Zhou, El Segundo, CA (US);
Jianjun Cao, Torrance, CA (US);
Alexander Lidow, Marina Del Rey, CA (US);
Robert Beach, La Crescenta, CA (US);
Alana Nakata, Redondo Beach, CA (US);
Robert Strittmatter, Tujunga, CA (US);
Guangyuan Zhao, Torrance, CA (US);
Seshadri Kolluri, San Jose, CA (US);
Yanping Ma, Torrance, CA (US);
Fang Chang Liu, Taiwan, TW;
Ming-Kun Chiang, Hsinchu, TW;
Jiali Cao, Torrance, CA (US);
Efficient Power Conversion Corporation, El Segundo, CA (US);
Abstract
A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.