The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Jul. 29, 2014
Applicant:

Efficient Power Conversion Corporation, El Segundo, CA (US);

Inventors:

Jianjun Cao, Torrance, CA (US);

Robert Beach, La Crescenta, CA (US);

Alexander Lidow, Marina Del Rey, CA (US);

Alana Nakata, Redondo Beach, CA (US);

Guangyuan Zhao, Torrance, CA (US);

Yanping Ma, Torrance, CA (US);

Robert Strittmatter, Tujunga, CA (US);

Michael A. De Rooji, Palm Springs, CA (US);

Chunhua Zhou, Torrance, CA (US);

Seshadri Kolluri, San Jose, CA (US);

Fang Chang Liu, Toufen Township, TW;

Ming-Kun Chiang, Hsinchu, TW;

Jiali Cao, Torrance, CA (US);

Agus Jauhar, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 27/085 (2006.01); H01L 29/40 (2006.01); H01L 21/8258 (2006.01); H01L 29/417 (2006.01); H01L 21/763 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/085 (2013.01); H01L 21/8258 (2013.01); H01L 29/402 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 21/763 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/41766 (2013.01); H01L 29/7787 (2013.01);
Abstract

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.


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