The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
Feb. 06, 2014
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Yuan-Chang Su, Luzhu Township, TW;
Shih-Fu Huang, Zhudong Township, TW;
Chia-Cheng Chen, Zhongli, TW;
Chia-Hsiung Hsieh, Yanshui Township, TW;
Tzu-Hui Chen, Taitung, TW;
Kuang-Hsiung Chen, Taoyuan, TW;
Pao-Ming Hsieh, Zhubei, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) a patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.