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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9165890 B1

PDFFull Text
Date of Patent:
Oct. 20, 2015

Filed:

Jul. 15, 2013

Chip package comprising alignment mark and method for forming the same

Applicant:

Xintec Inc., Jhongli, Taoyuan County, TW;

Inventors:

Yen-Shih Ho, Kaohsiung, TW;

Shih-Chin Chen, Zhubei, TW;

Yi-Ming Chang, Pingzhen, TW;

Chien-Hui Chen, Zhongli, TW;

Chia-Ming Cheng, Taipei, TW;

Wei-Luen Suen, New Taipei, TW;

Chen-Han Chiang, Luodong Township, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:

Liu & Liu

Primary Examiner:

Dilinh Nguyen

Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/78 (2013.01); H01L 23/3185 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05669 (2013.01); H01L 2224/0616 (2013.01); H01L 2224/06155 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/1416 (2013.01); H01L 2224/14155 (2013.01); H01L 2224/97 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15788 (2013.01);
Abstract

An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

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