The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2015
Filed:
Dec. 20, 2011
Pramod Malatkar, Chandler, AZ (US);
Drew W. Delaney, Chandler, AZ (US);
Rahul N. Manepalli, Chandler, AZ (US);
Dilan Seneviratne, Chandler, AZ (US);
Pramod Malatkar, Chandler, AZ (US);
Drew W. Delaney, Chandler, AZ (US);
Rahul N. Manepalli, Chandler, AZ (US);
Dilan Seneviratne, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A microelectronic package comprises a die () and a plurality of electrically conductive layers () and electrically insulating layers (), including a first electrically insulating layer () closer to the die than any other electrically insulating layer) and second () and third electrically insulating layers (). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTEfor the second electrically insulating layer is greater than CTEfor the first. CTEfor the third electrically insulating layer is less than CTEfor the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer () that is an outermost layer of the microelectronic package.