The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

May. 20, 2013
Applicant:

Xintec Inc., Jhongli, Taoyuan County, TW;

Inventors:

Po-Shen Lin, New Taipei, TW;

Tsang-Yu Liu, Zhubei, TW;

Yen-Shih Ho, Kaohsiung, TW;

Chih-Wei Ho, Zhongli, TW;

Yu-Min Liang, Zhongli, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); B81B 7/00 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 23/498 (2013.01); B81B 7/0077 (2013.01); H01L 21/78 (2013.01); H01L 24/94 (2013.01); H01L 27/14618 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01);
Abstract

Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.


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