The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2015
Filed:
Oct. 01, 2013
Globalfoundries Inc., Grand Cayman, KY;
Jing Wan, Malta, NY (US);
Andy Wei, Queensbury, NY (US);
Lun Zhao, Ballston Lake, NY (US);
Dae Geun Yang, Watervliet, NY (US);
Jin Ping Liu, Ballston Lake, NY (US);
Tien-Ying Luo, Clifton Park, NY (US);
Guillaume Bouche, Albany, NY (US);
Mariappan Hariharaputhiran, Ballston, NY (US);
Churamani Gaire, Clifton Park, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.