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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9142505 B1

PDFFull Text
Expired
Date of Patent:
Sep. 22, 2015

Filed:

Jun. 18, 2013

Method and apparatus for back end of line semiconductor device processing

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shin-Yi Yang, New Taipei, TW;

Hsiang-Huan Lee, Jhudong Township, TW;

Ming Han Lee, Taipei, TW;

Ching-Fu Yeh, Hsinchu, TW;

Pei-Yin Liou, Zhudong Township, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater & Matsil, L.L.P.

Primary Examiner:

Wael Fahmy

Assistant Examiner:

Sarah Salerno

Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76847 (2013.01); H01L 23/5329 (2013.01); H01L 23/53276 (2013.01); H01L 23/53295 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01);
Abstract

Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). A barrier layer comprising a bottom part and a side part is formed within an opening for a metal contact, wherein the bottom part comprises a graphene material, the side part comprises an amorphous carbon material and covers a sidewall of the opening, and the bottom part and the side part are formed at a same time. A capping layer comprising a first part and a second part is formed on a dielectric layer and a metal contact, wherein the first part comprises a graphene material, the second part of the capping layer comprises an amorphous carbon material on the dielectric layer, and the first part and the second part are formed at a same time.

Find Patent Forward Citations

Yang, Shin-Yi. (2015). Method and apparatus for back end of line semiconductor device processing (U.S. Patent No. 9142505). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9142505

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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