The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Jan. 24, 2013
Ravi Pillarisetty, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Van H. Le, Beaverton, OR (US);
Seung Hoon Sung, Beaverton, OR (US);
Jessica S. Kachian, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Han Wui Then, Portland, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Benjamin Chu-kung, Hillsboro, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Van H. Le, Beaverton, OR (US);
Seung Hoon Sung, Beaverton, OR (US);
Jessica S. Kachian, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Han Wui Then, Portland, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Benjamin Chu-Kung, Hillsboro, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.