The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Jan. 02, 2013
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries Inc., Grand Cayman, KY (US);
Takashi Ando, Tuckahoe, NY (US);
Maryjane Brodsky, Salt Point, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Min Dai, Mahwah, NJ (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Joseph F. Shepard, Jr., Poughkeepsie, NY (US);
Yanfeng Wang, Fishkill, NY (US);
Jinping Liu, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.