The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Jul. 02, 2013
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Stmicroelectronics, Inc., Coppell, TX (US);

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Grenoble Cedex, FR;

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Bruce B. Doris, Bewster, NY (US);

Ali Khakifirooz, Mountain View, CA (US);

Qing Liu, Guilderland, NY (US);

Laurent Grenouillet, Rives, FR;

Yannick Le Tiec, Crolles, FR;

Maud Vinet, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/76224 (2013.01); H01L 21/76283 (2013.01); H01L 21/0262 (2013.01);
Abstract

Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.


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