The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Jul. 31, 2012
Applicants:

Shih-ting Hung, Sanchong, TW;

Cheng-hung Chang, Hsin-Chu, TW;

Chen-yi Lee, Keelung, TW;

Chen-nan Yeh, Hsi-Chih, TW;

Chen-hua Yu, Hsin-Chu, TW;

Inventors:

Shih-Ting Hung, Sanchong, TW;

Cheng-Hung Chang, Hsin-Chu, TW;

Chen-Yi Lee, Keelung, TW;

Chen-Nan Yeh, Hsi-Chih, TW;

Chen-Hua Yu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.


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