The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2015
Filed:
Oct. 27, 2011
Maryjane Brodsky, Salt Point, NY (US);
Ming Cai, Hopewell Junction, NY (US);
Dechao Guo, Fishkill, NY (US);
William K. Henson, Beacon, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Yue Liang, Fishkill, NY (US);
Liyang Song, Wappingers Falls, NY (US);
Yanfeng Wang, Fishkill, NY (US);
Chun-chen Yeh, Clifton Park, NY (US);
MaryJane Brodsky, Salt Point, NY (US);
Ming Cai, Hopewell Junction, NY (US);
Dechao Guo, Fishkill, NY (US);
William K. Henson, Beacon, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Yue Liang, Fishkill, NY (US);
Liyang Song, Wappingers Falls, NY (US);
Yanfeng Wang, Fishkill, NY (US);
Chun-Chen Yeh, Clifton Park, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.