The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Jul. 01, 2004
William Volk, San Francisco, CA (US);
James Wiley, Menlo Park, CA (US);
Sterling Watson, Palo Alto, CA (US);
Sagar A. Kekare, Plano, TX (US);
Carl Hess, Los Altos, CA (US);
Paul Frank Marella, San Jose, CA (US);
Sharon Mccauley, San Jose, CA (US);
Ellis Chang, Saratoga, CA (US);
William Volk, San Francisco, CA (US);
James Wiley, Menlo Park, CA (US);
Sterling Watson, Palo Alto, CA (US);
Sagar A. Kekare, Plano, TX (US);
Carl Hess, Los Altos, CA (US);
Paul Frank Marella, San Jose, CA (US);
Sharon McCauley, San Jose, CA (US);
Ellis Chang, Saratoga, CA (US);
KLA-Tencor Technologies Corp., Milpitas, CA (US);
Abstract
Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.