The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2015
Filed:
Sep. 06, 2011
Yu-chih Liu, Taipei, TW;
Jing Ruei LU, Taipei, TW;
Wei-ting Lin, Taipei, TW;
Sao-ling Chiu, Hsinchu, TW;
Hsin-yu Pan, Taipei, TW;
Yu-Chih Liu, Taipei, TW;
Jing Ruei Lu, Taipei, TW;
Wei-Ting Lin, Taipei, TW;
Sao-Ling Chiu, Hsinchu, TW;
Hsin-Yu Pan, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method for assembling a flip chip ball grid array package includes mounting solder spheres to a ball grid array substrate, applying flux to a plurality of flip chip solder bumps provided on a diced wafer, aligning the ball grid array substrate over a chip on the diced wafer, picking and separating the chip from the diced wafer by urging the chip upwards towards the ball grid array substrate until the flip chip solder bumps on the chip come in contact with the ball grid array substrate, whereby the chip attaches to the ball grid array substrate in an upside-down orientation, and subjecting the chip and the ball grid array substrate to a thermal process whereby the solder spheres reflow and form solder balls and the flip chip solder bumps reflow and form solder joints between the chip and the ball grid array.