The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2014

Filed:

Mar. 15, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chao-Hsien Peng, Zhubei, TW;

Chi-Liang Kuo, Hsin-CHu, TW;

Hsiang-Huan Lee, Jhudong Township, TW;

Shau-Lin Shue, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/44 (2006.01); H01L 29/40 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76841 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug.


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