The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Sep. 22, 2011
Chia-pin Lin, Xinpu Township, TW;
Wen-sheh Huang, Hsinchu, TW;
Tian-choy Gan, Kluang Johor, MY;
Chia-lung Hung, Taipei, TW;
Hsien-chin Lin, Hsinchu, TW;
Shyue-shyh Lin, Hsinchu, TW;
Chia-Pin Lin, Xinpu Township, TW;
Wen-Sheh Huang, Hsinchu, TW;
Tian-Choy Gan, Kluang Johor, MY;
Chia-Lung Hung, Taipei, TW;
Hsien-Chin Lin, Hsinchu, TW;
Shyue-Shyh Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNor SiCNand the second nitride film is SiCN. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.