The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Jun. 23, 2011
Takaharu Yamano, Nagano, JP;
Hajime Iizuka, Nagano, JP;
Hideaki Sakaguchi, Nagano, JP;
Toshio Kobayashi, Nagano, JP;
Tadashi Arai, Nagano, JP;
Tsuyoshi Kobayashi, Nagano, JP;
Tetsuya Koyama, Nagano, JP;
Kiyoaki Iida, Nagano, JP;
Tomoaki Mashima, Nagano, JP;
Koichi Tanaka, Nagano, JP;
Yuji Kunimoto, Nagano, JP;
Takashi Yanagisawa, Nagano, JP;
Takaharu Yamano, Nagano, JP;
Hajime Iizuka, Nagano, JP;
Hideaki Sakaguchi, Nagano, JP;
Toshio Kobayashi, Nagano, JP;
Tadashi Arai, Nagano, JP;
Tsuyoshi Kobayashi, Nagano, JP;
Tetsuya Koyama, Nagano, JP;
Kiyoaki Iida, Nagano, JP;
Tomoaki Mashima, Nagano, JP;
Koichi Tanaka, Nagano, JP;
Yuji Kunimoto, Nagano, JP;
Takashi Yanagisawa, Nagano, JP;
Shinko Electric Industries Co., Ltd., Nagano, JP;
Abstract
A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.