The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2014
Filed:
Nov. 16, 2011
Chih-hao Chen, Hsin-Chu, TW;
Long Hua Lee, Taipei, TW;
Chun-hsing Su, New Taipei, TW;
Yi-lin Tsai, Tainan, TW;
Kung-chen Yeh, Taichung, TW;
Chung Yu Wang, Hsin-Chu, TW;
Jui-pin Hung, Hsinchu, TW;
Jing-cheng Lin, HsinChu, TW;
Chih-Hao Chen, Hsin-Chu, TW;
Long Hua Lee, Taipei, TW;
Chun-Hsing Su, New Taipei, TW;
Yi-Lin Tsai, Tainan, TW;
Kung-Chen Yeh, Taichung, TW;
Chung Yu Wang, Hsin-Chu, TW;
Jui-Pin Hung, Hsinchu, TW;
Jing-Cheng Lin, HsinChu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.