The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2014
Filed:
Jun. 04, 2012
Hsien-pin HU, Zhubei, TW;
Chen-hua Yu, Hsin-Chu, TW;
Shin-puu Jeng, Hsin-Chu, TW;
Shang-yun Hou, Jubei, TW;
Jing-cheng Lin, Hsin-Chu, TW;
Wen-chih Chiou, Miaoli, TW;
Hung-jung Tu, Hualien, TW;
Hsien-Pin Hu, Zhubei, TW;
Chen-Hua Yu, Hsin-Chu, TW;
Shin-Puu Jeng, Hsin-Chu, TW;
Shang-Yun Hou, Jubei, TW;
Jing-Cheng Lin, Hsin-Chu, TW;
Wen-Chih Chiou, Miaoli, TW;
Hung-Jung Tu, Hualien, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.