The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Jul. 21, 2011
Ken-hsien Hsieh, Taipei, TW;
Huang-yu Chen, Zhudong Township, Hsinchu County, TW;
Jhih-jian Wang, Taiping, TW;
Cheng Kun Tsai, Hsinchu, TW;
Tsong-hua Ou, Taipei, TW;
Wen-chun Huang, Tainan, TW;
Ru-gun Liu, Hsinchu, TW;
Ken-Hsien Hsieh, Taipei, TW;
Huang-Yu Chen, Zhudong Township, Hsinchu County, TW;
Jhih-Jian Wang, Taiping, TW;
Cheng Kun Tsai, Hsinchu, TW;
Tsong-Hua Ou, Taipei, TW;
Wen-Chun Huang, Tainan, TW;
Ru-Gun Liu, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.