The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Aug. 30, 2012
Christopher Boguslaw Kocon, Mountaintop, PA (US);
Steven Sapp, Felton, CA (US);
Paul Thorup, West Jordan, UT (US);
Dean Probst, West Jordan, UT (US);
Robert Herrick, Lehi, UT (US);
Becky Losee, Orem, UT (US);
Hamza Yilmaz, Saratoga, CA (US);
Christopher Lawrence Rexer, Moutaintop, PA (US);
Daniel Calafut, San Jose, CA (US);
Christopher Boguslaw Kocon, Mountaintop, PA (US);
Steven Sapp, Felton, CA (US);
Paul Thorup, West Jordan, UT (US);
Dean Probst, West Jordan, UT (US);
Robert Herrick, Lehi, UT (US);
Becky Losee, Orem, UT (US);
Hamza Yilmaz, Saratoga, CA (US);
Christopher Lawrence Rexer, Moutaintop, PA (US);
Daniel Calafut, San Jose, CA (US);
Fairchild Semiconductor Corporation, South Portland, ME (US);
Abstract
In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.