The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2014
Filed:
Jan. 04, 2011
Kun-hsien Lee, Tainan, TW;
Cheng-tung Huang, Kaohsiung, TW;
Wen-han Hung, Kaohsiung, TW;
Shyh-fann Ting, Kaohsiung County, TW;
Li-shian Jeng, Taitung, TW;
Meng-yi Wu, Kaohsiung Hsien, TW;
Tzyy-ming Cheng, Hsinchu, TW;
Kun-Hsien Lee, Tainan, TW;
Cheng-Tung Huang, Kaohsiung, TW;
Wen-Han Hung, Kaohsiung, TW;
Shyh-Fann Ting, Kaohsiung County, TW;
Li-Shian Jeng, Taitung, TW;
Meng-Yi Wu, Kaohsiung Hsien, TW;
Tzyy-Ming Cheng, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.