The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2013
Filed:
Feb. 27, 2008
Chun Chich Lin, Taichung, TW;
Yee-chia Yeo, Albany, CA (US);
Chien-chao Huang, Hsin-Chu, TW;
Chao-hsiung Wang, Hsin-Chu, TW;
Tien-chih Chang, Taipei, TW;
Chenming HU, Alamo, CA (US);
Fu-liang Yang, Hsin-Chu, TW;
Shih-chang Chen, Taoyuan, TW;
Mong-song Liang, Hsin-Chu, TW;
Liang-gi Yao, Hsin-Chu, TW;
Chun Chich Lin, Taichung, TW;
Yee-Chia Yeo, Albany, CA (US);
Chien-Chao Huang, Hsin-Chu, TW;
Chao-Hsiung Wang, Hsin-Chu, TW;
Tien-Chih Chang, Taipei, TW;
Chenming Hu, Alamo, CA (US);
Fu-Liang Yang, Hsin-Chu, TW;
Shih-Chang Chen, Taoyuan, TW;
Mong-Song Liang, Hsin-Chu, TW;
Liang-Gi Yao, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.