The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Oct. 23, 2009
Sinjae Lee, Kyoungki-do, KR;
Jingwan Kim, Kyoungki-do, KR;
Jihoon OH, Kyoungki-do, KR;
Jaehyun Lim, Kyoungki-do, KR;
Kyuwon Lee, Kyoungki-do, KR;
SinJae Lee, Kyoungki-do, KR;
JinGwan Kim, Kyoungki-do, KR;
JiHoon Oh, Kyoungki-do, KR;
JaeHyun Lim, Kyoungki-do, KR;
KyuWon Lee, Kyoungki-do, KR;
STATS ChipPAC, Ltd., Singapore, SG;
Abstract
A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.