The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Apr. 10, 2009
Sanka Ganesan, Chandler, AZ (US);
Yosuke Kanaoka, Ibaraki, JP;
Ram S. Viswanath, Phoenix, AZ (US);
Rajasekaran Swaminathan, Tempe, AZ (US);
Robert M. Nickerson, Chandler, AZ (US);
Leonel R. Arana, Phoenix, AZ (US);
John S. Guzek, Chandler, AZ (US);
Yoshihiro Tomita, Tsukuba, JP;
Sanka Ganesan, Chandler, AZ (US);
Yosuke Kanaoka, Ibaraki, JP;
Ram S. Viswanath, Phoenix, AZ (US);
Rajasekaran Swaminathan, Tempe, AZ (US);
Robert M. Nickerson, Chandler, AZ (US);
Leonel R. Arana, Phoenix, AZ (US);
John S. Guzek, Chandler, AZ (US);
Yoshihiro Tomita, Tsukuba, JP;
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.