The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2013
Filed:
Jul. 22, 2011
Gyu-hwan OH, Hwaseong-si, KR;
Sung-lae Cho, Gwacheon-si, KR;
Byoung-jae Bae, Hwaseong-si, KR;
Ik-soo Kim, Yongin-si, KR;
Dong-hyun Im, Hwaseong-si, KR;
Doo-hwan Park, Yongin-si, KR;
Kyoung-ha Eom, Incheon, KR;
Sung-un Kwon, Jeonju-si, KR;
Chul-ho Shin, Yongin-si, KR;
Sang-sup Jeong, Suwon-si, KR;
Gyu-Hwan Oh, Hwaseong-si, KR;
Sung-Lae Cho, Gwacheon-si, KR;
Byoung-Jae Bae, Hwaseong-si, KR;
Ik-Soo Kim, Yongin-si, KR;
Dong-Hyun Im, Hwaseong-si, KR;
Doo-Hwan Park, Yongin-si, KR;
Kyoung-Ha Eom, Incheon, KR;
Sung-Un Kwon, Jeonju-si, KR;
Chul-Ho Shin, Yongin-si, KR;
Sang-Sup Jeong, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.