The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
Jun. 11, 2010
Daniel Joseph Stillman, Garland, TX (US);
James L. Oborny, Sachse, TX (US);
William John Antheunisse, Rowlett, TX (US);
Norman J. Armendariz, Plano, TX (US);
Ramyanshu Datta, San Jose, CA (US);
Margaret Simmons-matthews, Richardson, TX (US);
Jeff West, Dallas, TX (US);
Daniel Joseph Stillman, Garland, TX (US);
James L. Oborny, Sachse, TX (US);
William John Antheunisse, Rowlett, TX (US);
Norman J. Armendariz, Plano, TX (US);
Ramyanshu Datta, San Jose, CA (US);
Margaret Simmons-Matthews, Richardson, TX (US);
Jeff West, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.