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For the Inventor, By the Inventor

Richardson, TX, United States of America

Margaret Simmons-Matthews

USPTO Granted Patents = 14 

Average Co-Inventor Count = 2.2

ph-index = 7

Forward Citations = 121(Granted Patents)


Company Filing History:

goldMedal14 out of 29,279 
 
Texas Instruments Corporation
 patents

Years Active: 2004-2014

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14 patents (USPTO):Explore Patents
1. 8815642 - Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies (2014-08-26),
2. 8759154 - TCE compensation for package substrates for reduced die warpage assembly (2014-06-24),
3. 8597978 - Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint (2013-12-03),
4. 8575758 - Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies (2013-11-05),
5. 8526186 - Electronic assembly including die on substrate with heat spreader having an open window on the die (2013-09-03),
6. 8471577 - Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate (2013-06-25),
7. 8344749 - Through carrier dual side loop-back testing of TSV die after die attach to substrate (2013-01-01),
8. 8344493 - Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips (2013-01-01),
9. 8313982 - Stacked die assemblies including TSV die (2012-11-20),
10. 8298863 - TCE compensation for package substrates for reduced die warpage assembly (2012-10-30),
11. 8288849 - Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint (2012-10-16),
12. 8227295 - IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV (2012-07-24),
13. 8097964 - IC having TSV arrays with reduced TSV induced stress (2012-01-17),
14. 6768212 - Semiconductor packages and methods for manufacturing such semiconductor packages (2004-07-27),
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