The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2013
Filed:
Aug. 19, 2011
Ming-tung Chang, Hsinchu County, TW;
Min-hsiu Tsai, Hsinchu County, TW;
Chih-mou Tseng, Chiayi County, TW;
Jen-yang Wen, Hualien County, TW;
Chien-mo LI, Taipei, TW;
Ming-Tung Chang, Hsinchu County, TW;
Min-Hsiu Tsai, Hsinchu County, TW;
Chih-Mou Tseng, Chiayi County, TW;
Jen-Yang Wen, Hualien County, TW;
Chien-Mo Li, Taipei, TW;
Global Unichip Corp., Hsinchu Science Park, Hsinchu, TW;
National Taiwan University, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu Science Park, Hsin-Chu, TW;
Abstract
In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.