Multi-gate semiconductor device with self-aligned epitaxial source and drain

Abstract

A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (H), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hproximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.