The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Dec. 17, 2008
Chien-liang Lin, Taoyuan County, TW;
Yu-ren Wang, Tai-Nan, TW;
Wu-chun Kao, Taoyuan County, TW;
Ying-hsuan LI, Pingtung, TW;
Ying-wei Yen, Miao- Li Hsien, TW;
Shu-yen Chan, Changhua County, TW;
Chien-Liang Lin, Taoyuan County, TW;
Yu-Ren Wang, Tai-Nan, TW;
Wu-Chun Kao, Taoyuan County, TW;
Ying-Hsuan Li, Pingtung, TW;
Ying-Wei Yen, Miao- Li Hsien, TW;
Shu-Yen Chan, Changhua County, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.