The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2012
Filed:
Oct. 10, 2006
Shenqing Fang, Fremont, CA (US);
Rinji Sugino, San Jose, CA (US);
Jayendra Bhakta, Sunnyvale, CA (US);
Takashi Orimoto, Sunnyvale, CA (US);
Hiroyuki Nansei, Fukushima-ken, JP;
Yukio Hayakawa, Fukushima-ken, JP;
Takayuki Maruyama, Fukushima-ken, JP;
Hidehiko Shiraiwa, San Jose, CA (US);
Kuo-tung Chang, Saratoga, CA (US);
Lei Xue, Sunnyvale, CA (US);
Meng Ding, Sunnyvale, CA (US);
Amol Ramesh Joshi, Sunnyvale, CA (US);
Youseok Suh, Cupertino, CA (US);
Harpreet Sachar, Milpitas, CA (US);
Shenqing Fang, Fremont, CA (US);
Rinji Sugino, San Jose, CA (US);
Jayendra Bhakta, Sunnyvale, CA (US);
Takashi Orimoto, Sunnyvale, CA (US);
Hiroyuki Nansei, Fukushima-ken, JP;
Yukio Hayakawa, Fukushima-ken, JP;
Takayuki Maruyama, Fukushima-ken, JP;
Hidehiko Shiraiwa, San Jose, CA (US);
Kuo-Tung Chang, Saratoga, CA (US);
Lei Xue, Sunnyvale, CA (US);
Meng Ding, Sunnyvale, CA (US);
Amol Ramesh Joshi, Sunnyvale, CA (US);
YouSeok Suh, Cupertino, CA (US);
Harpreet Sachar, Milpitas, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.