The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8138080 B1

Date of Patent:

Mar. 20, 2012

Filed:

Mar. 10, 2006

Integrated circuit package system having interconnect stack and external interconnect

Applicants:

Dario S. Filoteo, Jr., Singapore, SG;

Leo A. Merilo, Singapore, SG;

Philip Lyndon Cablao, Singapore, SG;

Emmanuel Espiritu, Singapore, SG;

Rachel Layda Abinan, Singapore, SG;

Allan Ilagan, Singapore, SG;

Inventors:

Dario S. Filoteo, Jr., Singapore, SG;

Leo A. Merilo, Singapore, SG;

Philip Lyndon Cablao, Singapore, SG;

Emmanuel Espiritu, Singapore, SG;

Rachel Layda Abinan, Singapore, SG;

Allan Ilagan, Singapore, SG;

Assignee:

Stats Chippac Ltd., Singapore, SG;

Attorney:

Mikio Ishimaru

Primary Examiner:

Ajay K Arora

Int. Cl.

CPC ...

H01L 21/44 (2006.01);

U.S. Cl.

CPC ...

Abstract

An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.

Find Patent Forward Citations

Quick Actions:

Filoteo, Jr., Dario. (2012). Integrated circuit package system having interconnect stack and external interconnect (U.S. Patent No. 8138080). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8138080

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile