The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2011

Filed:

Jul. 10, 2008
Applicants:

Michio Nakano, Hitachinaka, JP;

Shigeya Tanaka, Ibaraki, JP;

Yoshiyuki Momiyama, Hitachinaka, JP;

Takashi Hiroi, Yokohama, JP;

Kazuya Hayashi, Hitachinaka, JP;

Dai Fujii, Ibaraki, JP;

Takako Fujisawa, Tokai, JP;

Atsushi Ichige, Hitachinaka, JP;

Ichiro Kawashima, Hitachinaka, JP;

Inventors:

Michio Nakano, Hitachinaka, JP;

Shigeya Tanaka, Ibaraki, JP;

Yoshiyuki Momiyama, Hitachinaka, JP;

Takashi Hiroi, Yokohama, JP;

Kazuya Hayashi, Hitachinaka, JP;

Dai Fujii, Ibaraki, JP;

Takako Fujisawa, Tokai, JP;

Atsushi Ichige, Hitachinaka, JP;

Ichiro Kawashima, Hitachinaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.


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