The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Mar. 28, 2007
Kun-hsien Lee, Tainan, TW;
Cheng-tung Huang, Kaohsiung, TW;
Wen-han Hung, Kaohsiung, TW;
Shyh-fann Ting, Kaohsiung County, TW;
Li-shian Jeng, Taitung, TW;
Meng-yi Wu, Kaohsiung Hsien, TW;
Tzyy-ming Cheng, Hsinchu, TW;
Kun-Hsien Lee, Tainan, TW;
Cheng-Tung Huang, Kaohsiung, TW;
Wen-Han Hung, Kaohsiung, TW;
Shyh-Fann Ting, Kaohsiung County, TW;
Li-Shian Jeng, Taitung, TW;
Meng-Yi Wu, Kaohsiung Hsien, TW;
Tzyy-Ming Cheng, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsinchu, TW;
Abstract
A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.