The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Mar. 05, 2007
Li-shian Jeng, Taitung, TW;
Cheng-tung Huang, Kaohsiung, TW;
Shyh-fann Ting, Kaohsiung County, TW;
Wen-han Hung, Kaohsiung, TW;
Kun-hsien Lee, Tainan, TW;
Meng-yi Wu, Kaohsiung Hsien, TW;
Tzyy-ming Cheng, Hsinchu, TW;
Li-Shian Jeng, Taitung, TW;
Cheng-Tung Huang, Kaohsiung, TW;
Shyh-Fann Ting, Kaohsiung County, TW;
Wen-Han Hung, Kaohsiung, TW;
Kun-Hsien Lee, Tainan, TW;
Meng-Yi Wu, Kaohsiung Hsien, TW;
Tzyy-Ming Cheng, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsinchu, TW;
Abstract
A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.