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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7785950 B1

PDFFull Text
Expired
Date of Patent:
Aug. 31, 2010

Filed:

Nov. 10, 2005

Dual stress memory technique method and related structure

Applicants:

Sunfei Fang, LaGrangeville, NY (US);

Jun Jung Kim, Fishkill, NY (US);

Zhijiong Luo, Carmel, NY (US);

Hung Y. NG, New Milford, NJ (US);

Nivo Rovedo, LaGrangeville, NY (US);

Young Way Teh, Singapore, SG;

Inventors:

Sunfei Fang, LaGrangeville, NY (US);

Jun Jung Kim, Fishkill, NY (US);

Zhijiong Luo, Carmel, NY (US);

Hung Y. Ng, New Milford, NJ (US);

Nivo Rovedo, LaGrangeville, NY (US);

Young Way Teh, Singapore, SG;

Assignees:

International Business Machines Corporation, Armonk, NY (US);

Samsung Electronics Co., Ltd, Gyeonggi-do, KR;

Chartered Semiconductor Manufacturing Ltd, Singapore, SG;

Attorneys:

Joseph Petrokaitis

Hoffman Warnick LLC

Primary Examiner:

Hsien-ming Lee

Assistant Examiner:

Kevin Parendo

Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/469 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

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Fang, Sunfei. (2010). Dual stress memory technique method and related structure (U.S. Patent No. 7785950). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7785950

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