The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Sep. 28, 2007
Chen-hua Yu, Hsin-Chu, TW;
Cheng-tung Lin, Jhudong, TW;
Cheng-hung Chang, Hsin-Chu, TW;
Hsiang-yi Wang, Hsin-Chu, TW;
Chen-nan Yeh, Hsi-Chih, TW;
Chen-Hua Yu, Hsin-Chu, TW;
Cheng-Tung Lin, Jhudong, TW;
Cheng-Hung Chang, Hsin-Chu, TW;
Hsiang-Yi Wang, Hsin-Chu, TW;
Chen-Nan Yeh, Hsi-Chih, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.