The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Sep. 15, 2006
Keh-chiang Ku, Sindan, TW;
Chun-feng Nieh, Baoshan Township, TW;
Li-ping Huang, Taipei, TW;
Chih-chiang Wang, Hsin-Chu, TW;
Chien-hao Chen, Chuangwei Township, TW;
Hsun Chang, Hsin-Chu, TW;
Li-ting Wang, Tainan, TW;
Tze-liang Lee, Hsin-Chu, TW;
Shih-chang Chen, Hsin-Chu, TW;
Keh-Chiang Ku, Sindan, TW;
Chun-Feng Nieh, Baoshan Township, TW;
Li-Ping Huang, Taipei, TW;
Chih-Chiang Wang, Hsin-Chu, TW;
Chien-Hao Chen, Chuangwei Township, TW;
Hsun Chang, Hsin-Chu, TW;
Li-Ting Wang, Tainan, TW;
Tze-Liang Lee, Hsin-Chu, TW;
Shih-Chang Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.