The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Feb. 12, 2007
Fa-yuan Chang, Taipei, TW;
Tsung-mu Lai, Chu-Pei, TW;
Kai-chih Liang, Zhubei, TW;
Hua-shu Wu, Hsinchu, TW;
Chin-hsiang Ho, Hsinchu, TW;
Gwo-yuh Shiau, Hsinchu, TW;
Chu-wei Cheng, Pingjhen, TW;
Ming-chyi Liu, Hsinchu, TW;
Yuan-chih Hsieh, Hsinchu, TW;
Chia-shiung Tsai, Hsin-Chu, TW;
Nick Y. M. Shen, Chu-Pei, TW;
Ching-chung Pai, Taipei, TW;
Fa-Yuan Chang, Taipei, TW;
Tsung-Mu Lai, Chu-Pei, TW;
Kai-Chih Liang, Zhubei, TW;
Hua-Shu Wu, Hsinchu, TW;
Chin-Hsiang Ho, Hsinchu, TW;
Gwo-Yuh Shiau, Hsinchu, TW;
Chu-Wei Cheng, Pingjhen, TW;
Ming-Chyi Liu, Hsinchu, TW;
Yuan-Chih Hsieh, Hsinchu, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Nick Y. M. Shen, Chu-Pei, TW;
Ching-Chung Pai, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.