The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2010

Filed:

Oct. 25, 2006
Applicants:

Kun-hsien Lee, Tai-Nan, TW;

Cheng-tung Huang, Kao-Hsiung, TW;

Shyh-fann Ting, Tai-Nan, TW;

Wen-han Hung, Kao-Hsiung, TW;

Li-shian Jeng, Tai-Tung Hsien, TW;

Tzyy-ming Cheng, Hsin-Chu, TW;

Inventors:

Kun-Hsien Lee, Tai-Nan, TW;

Cheng-Tung Huang, Kao-Hsiung, TW;

Shyh-Fann Ting, Tai-Nan, TW;

Wen-Han Hung, Kao-Hsiung, TW;

Li-Shian Jeng, Tai-Tung Hsien, TW;

Tzyy-Ming Cheng, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.


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