The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Jan. 05, 2009
Michael P. Belyansky, Bethel, CT (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Unoh Kwon, Fishkill, NY (US);
Naim Moumen, Walden, NY (US);
Ravikumar Ramachandran, Pleasantville, NY (US);
James Kenyon Schaeffer, Wappingers Falls, NY (US);
Richard Wise, Newburgh, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
Hongwen Yan, Somers, NY (US);
Michael P. Belyansky, Bethel, CT (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Unoh Kwon, Fishkill, NY (US);
Naim Moumen, Walden, NY (US);
Ravikumar Ramachandran, Pleasantville, NY (US);
James Kenyon Schaeffer, Wappingers Falls, NY (US);
Richard Wise, Newburgh, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
Hongwen Yan, Somers, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.